1. Field of the Invention
The present invention relates in general to methods of fabricating a memory device, and in particular to methods of fabricating a memory device with a recess gate.
2. Description of the Related Art
In the rapidly evolving integrated circuit industry there is a development tendency toward high performance, miniaturization, and high operating speed. Additionally, dynamic random access memory (DRAM) fabrication methods have developed rapidly.
Typically, current dynamic random access memory DRAM cells include a transistor and a capacitor. Since the capacity of current DRAM has reached 512 MB and up to 1 GB, the sizes of memory cells and transistors have been narrowed to meet the demands for high integration, higher memory capacity and higher operating speeds. In conventional planar transistor technology, however, more useable surface area on a chip is required, and it is difficult to meet the previously mentioned demands. Accordingly, recessed gate and channel technology has been applied to DRAM fabrication with the goal of reducing the area occupied by the transistor and the capacitor on the semiconductor substrate. The conventional planar transistor technology requires a large amount of surface area on the chip, and cannot accomplish the demand for high integration. Conversely, the disadvantages of the conventional semiconductor memory cell can be improved by applying recessed vertical gate transistor (RVERT) technology to DRAM fabrication. And the RVERT technology is positioned to become a major semiconductor memory cell fabrication method.
For this reason, Applicant has disclosed the method for fabricating a recessed vertical gate transistor in U.S. patent application Ser. No. 11/145,728 entitled as “A method for forming a semiconductor device”. In this patent, Applicant has disclosed that rounded spacers, which are formed from a patterned pad layer and the trench top insulating layer are simultaneously used as a mask for etching the substrate to form a self-aligned recess of a recess gate.